(1) Field of the Invention
The present invention relates to semiconductor devices and methods for fabricating the same, and more particularly relates to semiconductor devices having field-effect transistors using high-dielectric-constant films as gate dielectrics and methods for fabricating the same.
(2) Description of Related Art
With an increasing degree of integration and operation speed of large scale integrated circuits (LSIs), metal insulator semiconductor (MIS) transistors serving as elementary elements of circuits have conventionally become finer according to the scaling law. When the dimensions of a MIS transistor, such as the gate length of a gate electrode thereof and the thickness of a gate dielectric thereof, are simultaneously miniaturized according to the scaling law, this can enhance the electrical characteristics of the MIS transistor. For example, in a case where the gate length of the gate electrode is set at 0.1 μm or less, the gate dielectric needs to have an equivalent oxide thickness (EOT) of approximately 2 nm or less.
However, in a case where a known gate dielectric made of silicon dioxide (SiO2) has a thickness of 2 nm or less, the leakage current due to a direct tunnel current passing through the gate dielectric increases, leading to the increased power consumption of an LSI. To cope with this, in recent years, a technique in which a high-dielectric-constant (high-k) film is used as a material of a gate dielectric has been suggested.
High-dielectric-constant materials typically represent dielectric materials having a higher dielectric constant than SiO2 having a dielectric constant of approximately 4 and include hafnium dioxide (HfO2), zirconium dioxide (ZrO2) or aluminum oxide (Al2O3). When such a high-dielectric-constant material is used for a gate dielectric, this allows the physical thickness of the gate dielectric to increase according to the amount of the dielectric constant increased. In view of the above, the leakage current produced due to the direct tunnel current can be reduced while the EOT of the gate dielectric is reduced.
MIS field-effect transistors using a high-dielectric-constant material as a material of gate dielectrics include those having a structure illustrated in FIG. 11 (see, for example, Japanese Unexamined Patent Publication No. 2003-69011). As illustrated in FIG. 11, a gate dielectric 104 composed of a first dielectric film 102 of SiO2 or SiON and a second dielectric film 103 of HfO2 is formed on a semiconductor substrate 101 made of silicon. A gate electrode 105 of doped polysilicon is formed on a part of the gate dielectric 104, and insulative sidewalls 106 are formed on parts of the top surface of the gate dielectric 104 located to both sides of the gate electrode 105. A source region 107 and a drain region 108 are formed in regions of the semiconductor substrate 101 located to both sides of the gate electrode 105 by impurity implantation. A channel region 109 is formed in a region of the semiconductor substrate 101 located under the gate dielectric 104 and between the source region 107 and the drain region 108.
This structure ensures that the gate dielectric 104 has an EOT of 2 nm or less. This can reduce the leakage current produced due to the direct tunnel current and prevent generation of fixed charges in the channel region 109 and deterioration in the mobility of carriers therein. As a result, the consumed power of the MIS transistor can be reduced and the current allowed to pass through the MIS transistor can be increased.
However, the known MIS transistor whose gate electrode 104 contains a high-dielectric-constant material has the following problems.
FIG. 12 illustrates a simulation result of an electric field intensity distribution in the channel region 109 along the line A-B in FIG. 11. Voltages are applied to a transistor under the following conditions: the gate voltage is 0 V and the drain voltage is 1 V. As obvious from FIG. 12, the electric field intensity in the semiconductor substrate 101 reaches its peak immediately below the end surface of the gate electrode 105 near the drain region 108 (GD).
FIG. 13 illustrates a result obtained by simulating, in the known MIS transistor illustrated in FIG. 11, the relationship between the EOT of the gate dielectric 104 and the maximum electric field intensity in the semiconductor substrate 101. FIG. 14 illustrates a result obtained by simulating, in the known MIS transistor illustrated in FIG. 11, the relationship between the EOT of the gate dielectric 104 and the leakage current flowing from the drain region 108 to the other region of the semiconductor substrate 101. In FIGS. 13 and 14, the gate length is 75 nm, the first dielectric film 102 has a thickness of 1 nm, the second dielectric film (high-dielectric-constant film) 103 has a thickness of 4 nm and different dielectric constants. Voltages are applied to the transistor under the following conditions: the gate voltage corresponding to the OFF state of the transistor is 0 V and the drain voltage is 1V.
As obvious from FIG. 13, the maximum electric field intensity in the semiconductor substrate 101 becomes higher with a decrease in the EOT of the gate dielectric 104. The reason for this is that the dielectric constant of the gate dielectric 104 is increased with a decrease in the EOT of the gate dielectric 104. As obvious from FIG. 14, the drain-to-substrate leakage current increases with a decrease in the EOT of the gate dielectric 104. The reason for this is that as illustrated in FIG. 13, the maximum electric field intensity in the semiconductor substrate 101 increases with a decrease in the EOT of the gate dielectric 104.
FIG. 15 illustrates a result obtained by simulating, in the known MIS transistor illustrated in FIG. 11, the relationship between the EOT of the gate dielectric 104 and the parasitic capacitance. In FIG. 15, the parasitic capacitance represents the mean value of the parasitic capacitances of the transistor corresponding to the ON and OFF states thereof. The gate length is 75 nm, the first dielectric film 102 has a thickness of 1 nm, and the second dielectric film 103 has a thickness of 4 nm and different dielectric constants. The operating frequency of the transistor is 10 MHz, and voltages are applied to the transistor under the following conditions: When the transistor is in an OFF state, the gate voltage is 0 V and the drain voltage is 1 V; and when the transistor is in an ON state, the gate voltage is 1V and the drain voltage is 1 V. As obvious from FIG. 15, the parasitic capacitance increases with a decrease in the EOT of the gate dielectric 104. The reason for this is that the capacitance of the transistor is proportional to the permittivity of the gate dielectric 104.
In view of the above, in a known MIS semiconductor device represented by that illustrated in FIG. 11, the electric field intensity increases in a part of a channel region located immediately below the end surface of a gate electrode near a drain with a decrease in the EOT of a gate dielectric. This increases the leakage current generated in the transistor, resulting in the increased power consumption. Furthermore, since the parasitic capacitance of the transistor increases with a decrease in the EOT, this prevents the operation speed of devices from increasing.